1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device and more particularly to a nonvolatile semiconductor memory device having a plurality of cell units each including a preset number of memory cells and select gate transistors on the drain and sources side as is represented by a NAND flash memory, for example.
2. Description of the Related Art
In the case of a NAND flash memory, generally, the write operation is realized by boosting channel potential with respect to a cell (non-selected cell or write inhibition cell) into which “1” is to be written. At this time, an erroneous write operation occurs if boost voltage applied to the word line is set high to a certain extent.
In the present NAND flash memory, the probability of occurrence of an erroneous write operation in a cell connected to a word line WL (for example, word line WL0) adjacent to a select gate line SGS on the source side is higher in comparison with that in a cell connected to another word line WL. This is considered because boost voltage applied to word line WL0 is temporarily set to excessively high voltage. Particularly, when data is written into a cell connected to word line WL0 and if data is not yet written into cells connected to the succeeding cells WL1 ˜, cells that obstruct formation of a channel are not present, and therefore, there occurs a possibility that boost voltage applied to word line WL0 is set to voltage higher than normal. For this reason, conventionally, there occurs a problem that an erroneous write operation with respect to the cell connected to word line WL0 tends to occur due to a gate-induced drain leakage (GIDL) current generated on the source side or source side injection current.
A nonvolatile semiconductor memory in which a lowering in the write inhibition potential due to a leakage current is prevented is already proposed (see, for example, Jpn. Pat. Appln. KOKAI Publication No. 2001-332093).